In recent years, imaging apparatuses such as video cameras and electronic still cameras have become generally widespread. In these imaging apparatuses (hereinafter referred to as “cameras”), charge coupled device (CCD) type solid-state imaging des sees and amplification type solid-state imaging devices are used. An amplification type solid-state imaging device guides an electric signal generated and stored by a photoelectric conversion unit such as a photodiode provided in a pixel on which light is incident to an amplification unit provided in the pixel and outputs the signal amplified by the amplification unit from the pixel. In the amplification type solid-state imaging device, a plurality of pixels is arranged in a two-dimensional matrix to form a pixel array unit. Among amplification-type solid-state imaging devices, there are, for example, CMOS type solid-state imaging devices and the like using complementary metal oxide semiconductor (CMOS) transistors.
In a conventional CMOS type solid-state imaging device, a scheme of sequentially reading electric signals generated and stored by photoelectric conversion units within each of pixels arranged in a two-dimensional matrix for each row using circuit units provided on the same substrate is adopted. In a CMOS type solid-state imaging device having a general monolithic structure (a structure manufactured by a single semiconductor substrate), peripheral circuits are arranged around a pixel array unit in which a plurality of pixels for converting incident light into electric signals are formed when viewed from a surface on which light is incident. These peripheral circuits are logic circuits such as a vertical scanning circuit, a horizontal scanning circuit, a column processing circuit, an output circuit, and the like. Wiring for transferring electric signals is provided for each column or each row between the pixel array unit and these peripheral circuits.
Meanwhile, recent CMOS type solid-state imaging devices are required to improve the data rate, the identicalness of the in-plane imaging performance, the high functionality, and the like. However, in the conventional CMOS type solid-state imaging device having a monolithic structure, it is difficult to improve the performance due to the speed limit, the density limit, and so on, in electric conduction in the plane direction. Also, in recent CMOS solid-state imaging devices, size reduction is also required, but it is difficult to reduce the area of the substrate plane because the peripheral circuits are arranged around the pixel array unit.
In view of this, a CMOS type solid-state imaging device configured as a single semiconductor device in which a semiconductor substrate having a pixel array in which a plurality of pixels are arranged, and a semiconductor substrate having the peripheral logic circuits for performing signal processing and the like and the memory circuit are stacked, and each of the semiconductor substrates are electrically connected has been proposed. By stacking a plurality of semiconductor substrates in this manner, improvement in performance and functionality, and size reduction in the CMOS solid-state imaging device are implemented.
In a CMOS type solid-state imaging device having a configuration in which a plurality of semiconductor substrates are stacked, pixels arranged in a pixel array are connected to corresponding circuits via corresponding connection electrode units. In other words, in the CMOS type solid-state imaging device having a configuration in which a plurality of semiconductor substrates are stacked, one connection electrode unit is provided for each pixel. In the CMOS Type solid-state imaging device having such a configuration, it is necessary to reliably connect the connection electrode units for electrically connecting each of the semiconductor substrates. In the CMOS type solid-state imaging device, if there is a connection failure in any connection electrode unit, the signal connection between the semiconductor substrates is interrupted, and it is impossible to exchange electric signals normally. Thus, in the CMOS type solid-state imaging device, if a connection failure occurs in any connection electrode unit, a state similar to the occurrence of a defect in the pixel at the position where the connection failure has occurred.
Generally, is difficult to completely eliminate defects of pixels in a solid-state imaging device. Therefore, if a pixel is defective in the solid-state imaging device in a camera, a process of treating the pixel at this position as a defective pixel and generating (interpolating) a signal of the defective pixel using signals output by pixels positioned around the defective pixel in image processing of the defective pixel correction to be executed thereafter is performed. By performing this defective pixel correction process, defective pixels in the solid-state imaging device are allowed to a certain extent in the camera.
On the other hand, technology for reducing the probability of occurrence of defective pixels due to a connection failure of the connection electrode unit has also been disclosed. For example, in Japanese Unexamined Patent Application, First Publication No. 2012-244331, technology relating to the arrangement of electrode pads in a CMOS type solid-state imaging device, having a configuration in which a first substrate in which a plurality of pixels are arranged and a second substrate having a read unit for reading signals of pixels are stacked is disclosed. In Japanese Unexamined Patent Application, First Publication No. 2012-244331, a plurality of pixels are divided into a plurality of regions for each unit pixel cell or each cell in which a plurality of pixels are integrated, and a plurality of connection pads, each of which is common to pixels included in each of the regions into which the pixels are divided, are assigned. With this configuration, in the CMOS type solid-state imaging device disclosed in Japanese Unexamined Patent Application, First Publication No. 2012-244331, the electric connection between the first substrate and the second substrate is secured by another connection pad within the same division region even when any connection pad in the same division region is not connected. In other words, in the CMOS type solid-state imaging device disclosed in Japanese Unexamined Patent Application, First Publication No. 2012-244331, the occurrence of a defective pixel due to a connection failure of the electrode pad is avoided by providing a plurality of paths for reading signals of pixels.